Cell Broadband Engine™ Overview

The Cell Broadband Engine™ (Cell BE) is a microprocessor jointly developed by IBM, Toshiba and Sony. The current chip is composed of one 64-bit PowerPC Processing Element (PPE) and 8 specialized co-processors called Synergistic Processing Elements (SPE). The PPE and SPEs are linked together by an internal high speed bus called Element Interconnect Bus (EIB).

The PowerPC Processing Element (PPE) follows the 64-bit PowerPC AS architecture, as the PowerPC 970 CPU (also known as the G5) and all recent IBM POWER™ processors also use. Like the 970, it can use the VMX (AltiVec) vector instructions to parallelize arithmetic operations.

The SPEs are composed of a Synergistic Processing Unit (SPU), and a SMF unit (DMA, MMU, and bus interface). A SPE is a RISC processor with 128-bit SIMD organization for single and double precision instructions. Each SPE contains a 256 KB instruction and data local memory area (called local store) which is visible to the PPE and can be addressed directly by software. The local store does not operate like a superscalar CPU cache since it is neither transparent to software nor does it contain hardware structures that predict what data to load.

The EIB is a circular bus made of two channels in opposite directions each. It enables communication between the PPE and SPEs. It is also connected to the L2 cache, the memory controller, and the FlexIO for external communications.

In the documentation section, you will find documents and links to other web sites that contain guides and extended documentation.